In the electronic component manufacturing industry, integrated circuits and other devices are typically fabricated in the form of slices, or wafers, of semiconductor material such as silicon, germanium or the like. Each of the slices contain a large number of individual circuits. The integrated circuits, as is well known in the art, maybe formatted or arranged on the wafer to facilitate subsequent dicing of the wafer into a sizeable number of integrated circuit chips.
Batch processing techniques have heretofore been employed in the fabrication of semiconductor wafers into integrated circuits. The practice of batch processing has numerous shortcomings. Not the least of which is the total elapsed time necessary to produce a finished slice. Long cycle times increase product cost. For example, when the cycle time for a process is longer than the backlog of orders for products produced by the process, it is necessary to forecast product orders and to begin the production of integrated circuit devices based thereon. If the forecast and production schedule are not reasonably in accord either a failure to meet delivery schedules results (customer dissatisfaction) or costly inventory is produced. Long cycle times are undesirable for numerous additional reasons known to the art. For example, in a batch process manufacturing system, a sizeable quantity of sub-standard, defective, or useless fully or partially completed product may be produced during the period between a failure and the introduction of an effective correction of the failure. A still further problem that results from the use of batch processing techniques is the deterioration of semiconductor wafers during the manufacturing process. The deterioration of the semiconductor wafers being due in large part to the repeated, human or machine handling of the wafers, the time duration of the complete process, and the relatively impossible task of processing the wafers through all steps of the system at the same rate. Namely, the accumulation of wafers between the faster and slower portions of the batch process manufacturing system and different times between such accumulation can frequently result in less uniform electrical characteristics of the product.
To obviate the problems of batch processing and efficiently produce high circuit density integrated circuit devices the art has gone in the direction of automating the production of integrated circuit devices.
Reference is made to U.S. Pat. No. 3,765,763, entitled "Automatic Slice Processing" granted Oct. 16, 1973. U.S. Pat. No. 3,765,763 discloses an electronic manufacturing system, wherein semiconductor slices are transported in serial fashion between a plurality of work stations. As the slices move through the system, each work station performs a separate manufacturing operation on each slice. The manufacturing operations are performed in immediate succession and within the same time interval so that the slices are processed rapidly and do not accumulate between the work stations. The slices are maintained in sequence throughout the system so that the operation of the system is more easily controlled.
In U.S. Pat. No. 3,765,763, the manufacturing system is computer controlled, the semiconductor slices are numbered and are operated on in sequence through the entire system. Each work station of the system performs its respective manufacturing operation within an optimum period of time so that slices do not accumulate at any point in the system.
Reference is made to U.S. Pat. No. 3,845,286, entitled "Manufacturing Control System For Processing Work Pieces" granted Oct. 29, 1974 to Messrs. Jesse Aronstein, W. E. Harding, and P. M. Zeiss, and to U.S. Pat. No. 3,889,355, entitled "Continuous Processing System" granted June 17, 1975 to Jesse Aronstein and Willian E. Harding. These patents disclose a manufacturing system and control system for the manufacturing line, where the manufacturing system utilizes a plurality of satellite functional processing stations or sectors, each capable of stand-alone operation. The wafer processing stations are interconnected by a wafer handler or conveyor which transports individual ones of the semiconductor wafers from one process sector to the next in response to the control system, so that the wafers will be sequenced through a prescribed sequence of sectors corresponding to the processing requirements for the semiconductor wafers.
Reference is made to U.S. Pat. No. 3,850,105, entitled "Apparatus for Transferring Articles Through Various Processing Sectors of a Manufacturing System" granted Nov. 26, 1974 to Jesse Aronstein, Arkady Leoff, John J. Murphy and Winfield S. Ruder. Disclosed is wafer handling and transport apparatus having particular utility when employed in a manufacturing system generally of the type disclosed in U.S. Pat. No. 3,889,355.
Reference is made to IBM Technical Disclosure Bulletin publication entitled "Pneumatic Distribution and Control System" by P. P Castrucci, Vol. 15, No. 6, November 1972, pages 1763 and 1764. The product control management system discussed in the IBM TDB publication is useful in the manufacture of large-scale integrated circuits. The system utilizes a computer automated, pneumatic transport hardware system to distribute and control the flow of semiconductor wafers through a manufacturing process environment. The system is designed for optimum product flow controlled via computer activation. The wafers are loaded into capsule cylinders which are directed between process sectors via pneumatic transport tubes. The outside of the cylinders are magnetic coated for recording product control information, such as process directions and fabrication data. The work in process is maintained at a smooth flow utilizing novel rotating inventory storage units.
The following publications and patents may be considered representative of the art disclosing the employment of a serial number, or other identifying indicia, on semiconductor wafers.
IBM Technical Disclosure Bulletin, entitled "Decoding and Encoding for Product Identification" by R. R. Jorgensen, Vol. 14, No. 4, September 1971, pages 1023 to 1025; IBM Technical Disclosure Bulletin, entitled "Identification of Wafers by Marginal Binary Notching and Template" by J. S. Jackson and W. E Wright, Vol. 15, No. 7, December 1972, pages 2773, 2774; U.S. Pat. No. 3,597,045, entitled "Automatic Wafer Identification System and Method" granted Aug. 3, 1971 to Einar S. Mathisen on application Ser. No. 837,765, filed June 30, 1969; U.S. Pat. No. 3,558,899 entitled "System and Method for Using Numerically Coded Etched Inidicia for Identification of Pieces of Semiconductor Material" granted Jan. 26, 1971 to Mark Morgan and Hans R. Rottmann on application Ser. No. 759,257, filed Aug. 30, 1968; and U.S. Pat. No. 3,562,536, entitled "Radiation Sensitive Semiconductor Wafer Identification System" granted Feb. 9, 1971 to Rolf H. Brunner and Ollie C. Woodard, on application Ser. No. 756,540 filed Aug. 30, 1968.
Reference is made to U.S. Pat. No. 3,976,330 granted Aug. 24, 1976 to J. P. Babinski et al., Ser. No. 618,654, entitled "Transport System for Semiconductor Wafer Multiprocessing Station System", filed Oct. 1, 1975, and of common assignee.
U.S. Pat. No. 3,976,330 discloses a dual bidirectional minimum volume self-centering air tract system for transporting semiconductor wafers or geometrically similar parts-in-process to and from processing tool stations in a random type manner and embodying controls to identify and collect treated wafers in segregated lots. The enclosed system is at a positive pressure to avoid ambient contamination. Said enclosed track system further embodies a means for the combined computerized control of individual wafer routing in the system, humidity, temperature, and particulate content of the fluid within and utilized by the transport system while supplying and receiving wafers to processing tool stations which may have a wide variation of ambient conditions. Further said transport system embodies among other features means for bidirectional travel with cross over intersections, directional control means, buffer sections and fluid vector means from a lower plenum for maintaining wafers centered on a fluidic cushion track so as to avoid edge contact of the wafer against any part of the apparatus and minimal backside or back flat face contact with the track membrane. The system also provides a means for sending wafers into the system and collecting processed pieces in suitable containers in lot or random form.
Reference is made to U.S. patent application Ser. No. 618,655, entitled "Fluidic Transport Intersection" filed Oct. 1, 1975 by J. P. Babinski, and of common assignee herewith.
U.S. patent application Ser. No. 618,655 discloses an apparatus and method for providing automatic or semiautomatic interconnections and intersections in a fluidic transportation system. In particular the teaching relates to the transportation of semiconductor wafers or slices between processing stations on a dual highway type system utilizing a fluidic cushion means whereby said wafers can be processed in a random manner and transported under a controlled environment dissimilar to the processing environment. However, the track, and system may be constructed into a multiplicity of configurations and is not limited to a dual or single track system.
The following publications and patents may be considered representative of the art disclosing apparatus for conveying, transporting, storing, positioning, processing, etc. semiconductor wafers.
U.S. Pat. No. 3,850,105, entitled "Apparatus for Transferring Articles Through Various Processing Sectors of A Manufacturing System," granted Nov. 26, 1974 to Jesse Aronstein, Arkady Leoff, John J. Murphy and Winfield S. Ruder on application Ser. No. 319,563, filed Dec. 29, 1972. U.S. Pat. No. 3,588,176, entitled "Article Transport System and Method", granted June 28, 1971 to Thomas M. Byrne and Arkady Leoff on Ser. No. 775,457, filed Nov. 13, 1968. U.S. Pat. No. 3,603,646, entitled "Semiconductor Wafer Air Slide with Controlled Wafer Motion", granted Sept. 7, 1971 to Arkady Leoff on application Ser. No. 5,454 filed Jan. 26, 1970. U.S. Pat. No. 3,649,081 entitled "Fluid Vibration Transport System", granted Mar. 14, 1972 to Robert Allen Johnson, Ervin H. Richards and Roy H. A. Watson on Ser. No. 108,815 filed Jan. 22, 1971. U.S. Pat. No. 3,625,384, entitled "Article Handling Device," granted Dec. 7, 1971 to Frank E. Boerger, Carlo Nuccio and Charles A. Rosboschil on application Ser. No. 762,896 filed Sept. 26, 1968. U.S. Pat. No. 3,631,758, entitled "Process for Grooving Fluid-Bearing Bars, and Resulting Articles" granted Jan. 4, 1972 to Cecil A. Lasch, Jr. on application Ser. No. 852,216, filed Aug. 22, 1969. U.S. Pat. No. 3,645,581, entitled "Apparatus and Method for Handling and Treating Articles", granted Feb. 29, 1972 to Cecil A. Lasch, Jr., George H. Bingham, Gerhard Berz and Earl G. Troyer on application Ser. No. 779,033, filed Nov. 26, 1968. U.S. Pat. No. 3,675,563, entitled "Semiconductor Processing Apparatus", granted July 11, 1972 to Claude G. Metreaud, on application Ser. No. 3,162, filed Jan. 15, 1970 U.S. Pat. No. 3,706,475, entitled "Air Slides", granted Dec. 19, 1972 to Carl Yakubowski, on application Ser. No. 128,277, filed Mar. 29, 1971. U.S. Pat. No. 3,707,944, entitled "Automatic Photoresist Apply and Dry Apparatus" granted Jan. 2, 1973, to Forrest Robert Grundon, Frank Harrison Masterson, Robert John Wagler and Fred Ernest Wustrau, on application Ser. No. 83,401, filed Oct. 23, 1970. U.S. Pat. No. 3,718,371, entitled "Fluid Bearing Track Structure and Components Thereof", granted Feb. 27, 1973 to Cecil A. Lasch Jr. on application Ser. No. 174,808, filed Aug. 25, 1971. U.S. Pat. No. 3,731,823, entitled "Wafer Transport System", granted May 8, 1973 to George R. Goth on application Ser. No. 148,731, filed June 1, 1971. U.S. Pat. No. 3,747,753, entitled "Fluid Bearing Apparatus and Method for Handling and Gaging Articles", granted July 24, 1973 to Alan G. Flint on application Ser. No. 220,336 filed Jan. 24, 1972. U.S. Pat. No. 3,785,027, entitled "Method of Producing Fluid Bearing Track Structure", granted Jan. 15, 1974 to Cecil A. Lasch, Jr. on application Ser. No. 280,273, filed Aug. 14, 1972. U.S. Pat. No. 3,853,313, entitled "Wafer Interlocking Transport", granted Dec. 10, 1974 to Henry Albert Appenzeller, Joseph Charles Miller and Vincent Shea on application Ser. No. 398,292 filed Sept. 17, 1973. U.S. Pat. No. 3,272,350, entitled "Method and Apparatus for Semiconductor Wafer Handling" granted Sept. 13, 1966 to Theodore Patrick, Peter E. Pflaumer and John W. Philbrick on application Ser. No. 399,200 filed Sept. 25, 1964. IBM TDB publication entitled "Transport of Substrates for Multilayer Deposition in a Vacuum" by B. I. Bertelsen, B. H. Parrish and G. Worthington, Vol. 10, No. 3, Aug. 1967, pages 198 and 199. IBM Technical Disclosure Bulletin Publication, entitled "Precision Wafer Orientation and Transfer System", by R. R. Jorgensen and H. A. Klein, Vol. 16, No. 9, February 1974, pages 2910 and 2911. U.S. Pat. No. 3.730,595, entitled "Linear Carrier Sender and Receiver" granted May 1, 1973 to Carl Yakubowski on application Ser. No. 203,374, filed Nov. 1, 1971.
IBM Technical Disclosure Bulletin publication, entitle "Vertical Wafer Storage System" R. J. Paul, W. S. Ruder and L. Sartorio, Vol. 16, No. 12, May 1974, pages 3917 and 3918.
IBM Technical Disclosure Bulletin publication, entitled "Wafer Loader/Unloader" by A. H. Bachmann and A. Kostenko, Jr., Vol. 17, No. 10, March 1975, pages 2908 and 2909.
IBM Technical Disclosure Bulletin publication, entitled "Article Handling System" by C. G. Metreand, Vol. 9, No. 7, December 1966 pages 953 and 954.
IBM Technical Disclosure Bulletin publication, entitled "Automatic Loading of Oxidation Boats" by G. R. Goth and R. B. Jerard, Vol. 14, No. 4, September 1971, page 1198.
IBM Technical Disclosure Bulletin publication, entitled "Air Track Buffer" by J. P. Babinski, Vol. 16, No. 2, July 1973, pages 469 and 470.